The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 30, 2011
Filed:
Jul. 08, 2009
Cihun-siyong Gong, Kaosiung, TW;
Ci-tong Hong, Xinzhuang, TW;
Muh-tian Shiue, Hsinchu, TW;
Kai-wen Yao, Hengchun Township, Pingtung County, TW;
Cihun-Siyong Gong, Kaosiung, TW;
Ci-Tong Hong, Xinzhuang, TW;
Muh-Tian Shiue, Hsinchu, TW;
Kai-Wen Yao, Hengchun Township, Pingtung County, TW;
National Central University, Jhongli, TW;
Abstract
A SRAM architecture includes a read/write control signal, a read/write control transistor block, an equalize transistor block, a 6-T SRAM cell, a sense amplifier block, a column selection transistor block and a write driver. The 6-T SRAM cell can store and write data. The sense amplifier block is used to read out the data stored in the 6-T SRAM cell correctly when the SRAM architecture performs a read operation and makes bit lines BL (bit line) and BLB() produce a minimum voltage difference. The column selection transistor block is used to select a column that the data is written in and read out. The write driver is used to perform a write operation to the 6-T SRAM cell of the column. The SRAM architecture can effectively increase the read SNM and dramatically reduce the power consumption.