The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 30, 2011
Filed:
Feb. 04, 2009
Masami Koketsu, Tokyo, JP;
Toshiaki Sawada, Nanae, JP;
Masami Koketsu, Tokyo, JP;
Toshiaki Sawada, Nanae, JP;
Renesas Electronics Corporation, Kawasaki-shi, JP;
Abstract
A technique for positioning a semiconductor chip and a mounting substrate with high precision using an alignment mark. In a semiconductor chip, a mark is formed in an alignment mark formation region over a semiconductor substrate in the same layer as an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. Pattern Pis formed in the same layer as a second layer wiring, pattern Pis formed in the same layer as a first layer wiring, pattern Pis formed in the same layer as a gate electrode, and pattern Pis formed in the same layer as an element isolation region.