The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 30, 2011
Filed:
Oct. 25, 2007
Sung-hoon Yang, Yongin-si, KR;
So-woon Kim, Suwon-si, KR;
Chong-chul Chai, Seoul, KR;
Joo-ae Youn, Seongnam-si, KR;
Kyoung-ju Shin, Hwaseong-si, KR;
Yeon-ju Kim, Suwon-si, KR;
Soo-wan Yoon, Suwon-si, KR;
Sung-Hoon Yang, Yongin-si, KR;
So-Woon Kim, Suwon-si, KR;
Chong-Chul Chai, Seoul, KR;
Joo-Ae Youn, Seongnam-si, KR;
Kyoung-Ju Shin, Hwaseong-si, KR;
Yeon-Ju Kim, Suwon-si, KR;
Soo-Wan Yoon, Suwon-si, KR;
Samsung Electronics Co., Ltd., Suwon-si, KR;
Abstract
A display substrate having a fan-out and a method for manufacturing the display substrate are disclosed. The fan-out includes an insulating substrate, a first line, a second line, a resistance control pattern, and first and second detour pattern. The first line is disposed on the insulating substrate and is connected to a pad. The second line is formed from the same layer as the first line and is connected to a thin-film transistor (TFT). The resistance control pattern is formed from a different layer than the first and second lines. The first and second detour patterns are formed from a different layer than the first and second lines and the resistance control pattern, and connect the first and second lines with the resistance control pattern, respectively.