The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2011

Filed:

Dec. 30, 2006
Applicants:

Fritz Kirscht, Berlin, DE;

Kamel Ounadjela, Belmont, CA (US);

Jean Patrice Rakotoniana, Berlin, DE;

Dieter Linke, Berlin, DE;

Inventors:

Fritz Kirscht, Berlin, DE;

Kamel Ounadjela, Belmont, CA (US);

Jean Patrice Rakotoniana, Berlin, DE;

Dieter Linke, Berlin, DE;

Assignee:

Calisolar, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Techniques are here disclosed for a solar cell pre-processing method and system for annealing and gettering a solar cell semiconductor wafer having an undesirably high dispersion of transition metals, impurities and other defects. The process forms a surface contaminant layer on the solar cell semiconductor (e.g., silicon) wafer. A surface of the semiconductor wafer receives and holds impurities, as does the surface contaminant layer. The lower-quality semiconductor wafer includes dispersed defects that in an annealing process getter from the semiconductor bulk to form impurity cluster toward the surface contaminant layer. The impurity clusters form within the surface contaminant layer while increasing the purity level in wafer regions from which the dispersed defects gettered. Cooling follows annealing for retaining the impurity clusters and, thereby, maintaining the increased purity level of the semiconductor wafer in regions from which the impurities gettered. Multicrystalline semiconductor wafers having grain boundaries with impurities may also undergo the annealing and gettering of dispersed defects to the grain boundaries, further increasing the semiconductor substrate purity levels.


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