The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8006001 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 23, 2011

Filed:

Sep. 22, 2004
Applicants:

Jackson Lloyd Ellis, Fort Collins, CO (US);

Kurt Jay Kastein, Fort Collins, CO (US);

Praveen Viraraghavan, Fort Collins, CO (US);

Inventors:

Jackson Lloyd Ellis, Fort Collins, CO (US);

Kurt Jay Kastein, Fort Collins, CO (US);

Praveen Viraraghavan, Fort Collins, CO (US);

Assignee:

LSI Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/10 (2006.01); G06F 13/14 (2006.01);
U.S. Cl.
CPC ...
Abstract

A mechanism is provided for removal of instructions for context re-evaluation. The mechanism receives an external request to perform the instruction remove. In response to this external request, the mechanism next determines when the state of the system is stable for allowing the instruction remove. Then the mechanism creates a first event to remove a current data instruction in a DMA, if present, and merge it back onto the list of pending contexts from where it originated. The mechanism waits for feedback that the first event has completed. Then the mechanism creates a second event to remove a pending data instruction that was chosen to be next in the DMA, if present, and merge it back onto the list of pending contexts from where it originated. Finally the mechanism waits for feedback that the second event has completed. The merging of contexts back onto the pending list from where they originated aborts any activity related to preparing further data instructions and holds off further decisions about which context to DMA next until the instruction remove procedure is completed and a correct priority decision can be made again. The result of the ability to remove instructions is that the system can respond to changing conditions on a protocol bus and be capable of preparing the best DMA instructions possible for optimizing the performance on the protocol bus.


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Ellis, Jackson. (2011). Method and apparatus for manipulating direct memory access transfers (U.S. Patent No. 8006001). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8006001

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