The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 2011
Filed:
Oct. 22, 2004
Applicant:
Glenn C. Steiner, Los Altos, CA (US);
Inventor:
Glenn C. Steiner, Los Altos, CA (US);
Assignee:
Xilinx, Inc., San Jose, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03D 3/24 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method for adjusting a clock for a jitter sensitive circuit begins by determining a low noise phase region of a primary clock. The method then continues by adjusting phase of an auxiliary clock such that a transition of the auxiliary clock falls within the low noise phase region of the primary clock to produce an adjusted auxiliary clock.
Steiner, Glenn. (2011). Clock and clock adjustment circuit for minimum jitter (U.S. Patent No. 8005181). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8005181
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile