The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2011

Filed:

May. 21, 2009
Applicants:

Rong Pan, Sunnyvale, CA (US);

Ming Zhang, San Jose, CA (US);

Chiara Piglione, San Jose, CA (US);

Valentina Alaria, San Francisco, CA (US);

Inventors:

Rong Pan, Sunnyvale, CA (US);

Ming Zhang, San Jose, CA (US);

Chiara Piglione, San Jose, CA (US);

Valentina Alaria, San Francisco, CA (US);

Assignee:

Cisco Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 12/54 (2006.01);
U.S. Cl.
CPC ...
Abstract

In one embodiment, apparatus and methods for apparatus and methods for fair bandwidth allocation are disclosed. In one embodiment, a method includes (i) determining a drop probability for each of a plurality of classes of packets being dropped or admitted to a queue, wherein each drop probability is based on a weighted fair bandwidth allocation process that is performed with respect to the plurality of classes and a plurality of packet arrival rates and predefined weights for such classes; and (ii) dropping a particular packet or admitting such particular packet to the queue based on the drop probability for such particular packet's class, wherein such dropping or admitting operation is further based on one or more drop precedence factors that are also determined periodically for each class if such one or more drop precedence factors are selected for such each class. In other embodiments, the invention pertains to an apparatus having one or more processors and one or more memory, wherein at least one of the processors and memory are adapted for performing the above described method operations.


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