The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2011

Filed:

Mar. 12, 2010
Applicants:

Mikio Ogawa, Yokohama, JP;

Norihiro Fujita, Yokohama, JP;

Hiroshi Nakamura, Fujisawa, JP;

Inventors:

Mikio Ogawa, Yokohama, JP;

Norihiro Fujita, Yokohama, JP;

Hiroshi Nakamura, Fujisawa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor memory device includes a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp transistor operative to clamp a bit line voltage. The sense amp circuit is operative to detect data in a selected memory cell via the clamp transistor and the bit line. The sense amp circuit is operative to read data from the selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of the clamp transistor. Different control voltages are applied to the gate of the clamp transistor in the first and second read cycles.


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