The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 2011
Filed:
Feb. 24, 2005
Fumio Akama, Tokyo-To, JP;
Ryoichi Yoshimura, Tokyo-To, JP;
Hideaki Tanaka, Tokyo-To, JP;
Hitoshi Uchida, Tokyo-To, JP;
Koji Okano, Tokyo-To, JP;
Fumio Akama, Tokyo-To, JP;
Ryoichi Yoshimura, Tokyo-To, JP;
Hideaki Tanaka, Tokyo-To, JP;
Hitoshi Uchida, Tokyo-To, JP;
Koji Okano, Tokyo-To, JP;
Nippon Mektron, Ltd., Tokyo-To, JP;
Abstract
A method for easily making a barrier for preventing overflow of interlayer insulating resin in a cable-fitted multi-layer FPC that uses bumps for connecting the layers, and a barrier having a structure that can easily be made. In a method for manufacturing a multi-layer flexible printed circuit board including a circuit section, a cable section that is connected to the circuit section, the circuit section having a multi-layer structure of insulating resin arranged between multiple layers of metal foil, a barrier, that stops the insulating resin from overflowing, has a two-row configuration and is formed on a metal foil that constitutes an outermost conductive layer in the multi-layer flexible printed circuit board, and the metal foil and the insulating resin are laminated to form the multi-layer flexible printed circuit board.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile