Semiconductor integrated circuit and transmitter apparatus having the same

Abstract

A semiconductor integrated circuit (D) for receiving a parallel data signal and a first clock signal and outputting a serial data signal and a second clock signal, wherein a first clock generation circuit () produces a third clock signal obtained by multiplying the first clock signal by X/Y. A second clock generation circuit () has a variable transmission characteristic, and produces a fourth clock signal obtained by multiplying the third clock signal by N. A parallel/serial conversion section () converts the parallel data signal, which has been converted by a scaler (), to the serial data signal in synchronism with the fourth clock signal. A frequency divider () produces a fifth clock signal obtained by dividing a frequency of the fourth clock signal by N. A selector () selectively outputs, as the second clock signal, one of the third and fifth clock signals.