The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2011

Filed:

Jun. 17, 2008
Applicants:

Gil-sub Kim, Daegu, KR;

Yong-il Kim, Hwaseong-si, KR;

Jong-seop Lee, Osan-si, KR;

Jai-kyun Park, Hwaseong-si, KR;

Yun-sung Lee, Seongnam-si, KR;

Nam-jung Kang, Suwon-si, KR;

Inventors:

Gil-sub Kim, Daegu, KR;

Yong-il Kim, Hwaseong-si, KR;

Jong-seop Lee, Osan-si, KR;

Jai-kyun Park, Hwaseong-si, KR;

Yun-sung Lee, Seongnam-si, KR;

Nam-jung Kang, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods of manufacturing a semiconductor device having an RCAT are provided. The method includes forming a first recess having a first depth formed in an active region of a semiconductor substrate, and a second recess having a second depth that is less than the first depth formed in an isolation layer. The depth of the second recess is decreased by removing the isolation layer from the upper surface of the isolation layer by a desired thickness. A gate dielectric layer is formed on an inner wall of the first recess and a gate is formed on the gate dielectric layer.


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