The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 16, 2011

Filed:

Dec. 05, 2005
Applicants:

Mihail Iotov, San Jose, CA (US);

David Neto, Toronto, CA;

Pouyan Djahani, Toronto, CA;

David Karchmer, Los Altos, CA (US);

Kumara Tharmalingam, Mountain View, CA (US);

Inventors:

Mihail Iotov, San Jose, CA (US);

David Neto, Toronto, CA;

Pouyan Djahani, Toronto, CA;

David Karchmer, Los Altos, CA (US);

Kumara Tharmalingam, Mountain View, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/45 (2006.01); G06F 17/50 (2006.01); G06F 9/455 (2006.01);
U.S. Cl.
CPC ...
Abstract

During compilation of a user logic design in a first type of programmable logic device (e.g., an FPGA), a log is kept of at least certain steps where choices are made. When that logic design is migrated to another type of programmable logic device (e.g., a mask-programmable logic device) the logged steps are taken into account to make sure that the same choices are made, so that the target device is functionally equivalent to the original device.


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