The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2011
Filed:
Oct. 23, 2007
Nafira Daud, Pleasanton, CA (US);
Geping Liu, Sunnyvale, CA (US);
San Wong, Cupertino, CA (US);
Lawrence David Smith, San Jose, CA (US);
Nafira Daud, Pleasanton, CA (US);
Geping Liu, Sunnyvale, CA (US);
San Wong, Cupertino, CA (US);
Lawrence David Smith, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A method for optimizing pin selection for an integrated circuit is provided. Pin locations are mapped to a vector. The mutual inductive relationships between pins of the integrated circuit are captured into a matrix. The matrix contains the data of how a signal state of each pin is affected by the toggling of other pins within the I/O bank. The pin locations and the crosstalk matrix are combined to characterize the impact of the crosstalk on the pins for the pin placement. Thereafter, a user may decide to alter the pin placement or alter the sampling interval for the pin to avoid sampling the pin when the crosstalk may affect the signal integrity. The method may be applied for multiple simultaneous switching noise cause mechanisms impacting the signal integrity. In this embodiment, a worst case cause mechanism from the individually quantified cause mechanisms is determined by comparing an impact of each of the cause mechanisms.