The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2011
Filed:
Jul. 15, 2008
Kalpesh Hira, Austin, TX (US);
Neil A. Panchal, Round Rock, TX (US);
Kalpesh Hira, Austin, TX (US);
Neil A. Panchal, Round Rock, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Latches in a net of a simulated integrated circuit design are initialized to known logical states prior to application of a reset signal at the beginning of the simulation. The logical states may be set by generating a list of the latches, sorting them in random order, and then dividing them into two groups based on the random order with high and low logical states respectively assigned to the two groups. In a specific implementation the latch states are set using an HDL force command prior to applying the reset signal, and the force command is removed after applying the reset signal using an HDL release command. If the circuit description is a gate-level netlist, then logical states of gates within the storage elements are also set.