The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2011
Filed:
Jul. 24, 2008
Hideya Murai, Tokyo, JP;
Kentaro Mori, Tokyo, JP;
Shintaro Yamamichi, Tokyo, JP;
Masaya Kawano, Kanagawa, JP;
Takehiko Maeda, Kanagawa, JP;
Kouji Soejima, Kanagawa, JP;
Hideya Murai, Tokyo, JP;
Kentaro Mori, Tokyo, JP;
Shintaro Yamamichi, Tokyo, JP;
Masaya Kawano, Kanagawa, JP;
Takehiko Maeda, Kanagawa, JP;
Kouji Soejima, Kanagawa, JP;
NEC Corporation, Tokyo, JP;
Renesas Electronics Corporation, Kanagawa, JP;
Abstract
Semiconductor device has a semiconductor chip embedded in an insulating layer. A semiconductor device comprises a semiconductor chip formed to have external connection pads and a positioning mark that is for via formation; an insulating layer containing a non-photosensitive resin as an ingredient and having a plurality of vias; and wiring electrically connected to the external connection pads through the vias and at least a portion of which is formed on the insulating layer. The insulating layer is formed to have a recess in a portion above the positioning mark. The bottom of the recess is the insulating layer alone. Vias have high positional accuracy relative to the mark.