The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2011
Filed:
May. 06, 2009
Gautham Viswanadam, Singapore, SG;
Gautham Viswanadam, Singapore, SG;
Other;
Abstract
A method and apparatus for manufacturing an integrated circuit (IC) device () is disclosed. A wafer () is first provided having a first or top surface and a second or bottom surface. The wafer may be a blank polished or unpolished silicon wafer or the like. High aspect ratio micro-structures () that are specifically designed to provide a die level interconnect configuration and mapping, are provided on the first blank surface () of the wafer. The wafer with preformed conductive interconnect microstructures () are further processed for device fabrication, for example, at the wafer fabrication facilities. Once the front side () devices are fabricated, the silicon material () is then removed from a second side () of the device wafer (), opposite the first side, to expose the high temperature conductive interconnect microstructures (). Contacts are formed on the second side of the device wafer using conductive metal. These contacts are electrically connected to the interior of the microstructures and thereby electrically connect with the functional device (). The dies (()),(()) are separated along the separation zones () between the dies to produce individualized functional and packaged dies, each of which serves as a fully packaged IC device ().