The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 09, 2011
Filed:
May. 21, 2009
Motoyasu Terao, Hinode, JP;
Satoru Hanzawa, Hachioji, JP;
Hitoshi Kume, Musashino, JP;
Minoru Ogushi, Kodaira, JP;
Yoshitaka Sasago, Tachikawa, JP;
Masaharu Kinoshita, Kokubunji, JP;
Norikatsu Takaura, Tokyo, JP;
Motoyasu Terao, Hinode, JP;
Satoru Hanzawa, Hachioji, JP;
Hitoshi Kume, Musashino, JP;
Minoru Ogushi, Kodaira, JP;
Yoshitaka Sasago, Tachikawa, JP;
Masaharu Kinoshita, Kokubunji, JP;
Norikatsu Takaura, Tokyo, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.