The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2011

Filed:

Jul. 23, 2008
Applicants:

Jerrold S. Zdenek, Maricopa, AZ (US);

Joseph Julicher, Maricopa, AZ (US);

Sean Steedman, Phoenix, AZ (US);

Vivien Delport, Chandler, AZ (US);

Inventors:

Jerrold S. Zdenek, Maricopa, AZ (US);

Joseph Julicher, Maricopa, AZ (US);

Sean Steedman, Phoenix, AZ (US);

Vivien Delport, Chandler, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A processor device has a data memory with a linear address space, the data memory being accessible through a plurality of memory banks. At least a subset of the memory banks are organized such that each memory bank of the subset has at least a first and second memory area, wherein no consecutive memory block is formed by the second memory areas of a plurality of consecutive memory banks. An address adjustment unit is provided which, when a predefined address range is used, translates an address within the predefined address range to access said second memory areas such that through the address a plurality of second memory areas form a continuous linear memory block.


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