The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2011

Filed:

Jan. 06, 2009
Applicants:

Jean L. Calvignac, Raleigh, NC (US);

Chih-jen Chang, Apex, NC (US);

Joseph F. Logan, Raleigh, NC (US);

Fabrice J. Verplanken, La Gaude, FR;

Daniel Wind, Drap, FR;

Inventors:

Jean L. Calvignac, Raleigh, NC (US);

Chih-jen Chang, Apex, NC (US);

Joseph F. Logan, Raleigh, NC (US);

Fabrice J. Verplanken, La Gaude, FR;

Daniel Wind, Drap, FR;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/08 (2006.01); H04L 12/28 (2006.01); H04L 12/54 (2006.01);
U.S. Cl.
CPC ...
Abstract

A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.


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