Optimized phase alignment in analog-to-digital conversion of video signals

Abstract

A digital video system () is disclosed, in which an analog input video signal is sampled at an optimum sample phase (P), and converted to a digital datastream for display. A phase-locked loop () generates a plurality of sample clock phases. One of the sample clock phases (P) is applied to an analog-to-digital converter (), which digitizes the analog input video signal accordingly. Phase alignment circuitry () is provided that includes three sample-and-hold circuits () that sample the analog input video signal, in parallel with the analog-to-digital converter (), at times before, at, and after the current sample clock phase used by the analog-to-digital converter (). The earlier and later sampled voltages are compared against the current sampled voltages to generate difference voltages that are each compared against a threshold voltage (V). The numbers of times that the difference voltages exceed the threshold voltage over a field or frame is analyzed according to various techniques, to determine whether and in which direction to adjust the position of the current sample clock phase within the pixel period.