The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2011

Filed:

Jul. 26, 2007
Applicants:

Yi Wu, Santa Clara, CA (US);

Kenan Yu, San Jose, CA (US);

Inventors:

Yi Wu, Santa Clara, CA (US);

Kenan Yu, San Jose, CA (US);

Assignee:

Oracle America, Inc., Redwood City, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/10 (2006.01); H01L 29/73 (2006.01);
U.S. Cl.
CPC ...
Abstract

A filler cell for use in fabricating an integrated circuit. The filler cell couples a power supply rail of an adjacent logic cell to a power supply rail of another adjacent logic cell. The filler cell also has a diode to bleed charge accumulated on the power rails of the adjacent logic cells to the substrate. The diode is reverse biased during normal integrated circuit operation. A method for fabricating an integrated circuit with a power grid. At least one filler cell is placed on the integrated circuit to bleed away charge accumulated on the power grid during the fabrication of the integrated circuit. The filler cell is connected to a supply rail of an adjacent logic cell.


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