The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2011

Filed:

May. 09, 2007
Applicants:

Sudeep Biswas, Delhi, IN;

Angelo Di Sena, Castello di Cisterna, IT;

Domenico Manna, Acerra, IT;

Inventors:

Sudeep Biswas, Delhi, IN;

Angelo Di Sena, Castello di Cisterna, IT;

Domenico Manna, Acerra, IT;

Assignees:

STMicroelectronics S.R.L., Agrate Brianza (MB), IT;

STMicroelectronics Pvt. Ltd., Greater Noida (UP), IN;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/10 (2006.01); G06F 12/12 (2006.01); G06F 11/20 (2006.01);
U.S. Cl.
CPC ...
Abstract

A solution for managing a storage device based on a flash memory is proposed. A corresponding method starts with the step for mapping a logical memory space of the storage device (including a plurality of logical blocks) on a physical memory space of the flash memory (including a plurality of physical blocks, which are adapted to be erased individually). The physical blocks include a set of first physical blocks (corresponding to the logical blocks) and a set of second—or spare—physical blocks (for replacing each bad physical block that is unusable). The method continues by detecting each bad physical block. Each bad physical block is then discarded, so to prevent using the bad physical block for mapping the logical memory space.


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