The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 02, 2011
Filed:
Jul. 05, 2009
Kia Silverbrook, Balmain, AU;
Matthew John Underwood, Balmain, AU;
Nicholas Damon Ridley, Balmain, AU;
Paul Lapstun, Balmain, AU;
Peter Charles Boyd Henderson, Balmain, AU;
Zhenya Alexander Yourlo, Balmain, AU;
Alireza Moini, Balmain, AU;
Kia Silverbrook, Balmain, AU;
Matthew John Underwood, Balmain, AU;
Nicholas Damon Ridley, Balmain, AU;
Paul Lapstun, Balmain, AU;
Peter Charles Boyd Henderson, Balmain, AU;
Zhenya Alexander Yourlo, Balmain, AU;
Alireza Moini, Balmain, AU;
Silverbrook Research Pty Ltd, Balmain, New South Wales, AU;
Abstract
A photodetecting circuit is disclosed which includes a photodetector for generating a signal in response to incident light, a storage node, transfer and reset transistors and an output circuit. The storage node has first and second node terminals. The second node terminal is connected to a compensation signal during a read period of the photodetection circuit. The transfer transistor is disposed intermediate the first node terminal of the storage node and the photodetector and is for electrically connecting the first node terminal and the photodetector during an integration period upon receiving a transfer signal to a gate of the transfer transistor, allowing charge stored in the storage node to change based on the signal of the photodetector. The reset transistor has a control node for receiving a reset signal, a first terminal for receiving a reset voltage, and a second terminal electrically connected to the first node terminal, such that the reset voltage is supplied to the first node terminal when the reset signal is asserted at a gate of the reset transistor. The output circuit generates an output signal during the read period of the photodetecting circuit. The output signal is at least partially based on a voltage at the first terminal. The compensation signal is a logically negated version of the transfer signal.