Low-jitter phase-locked loop

Abstract

A phase-locked loop (PLL) with a decreased frequency tuning gain Kand a loop filter using capacitor multiplication technique to get high chip area efficiency. To get decreased frequency tuning gain, K, a voltage to current converter in a voltage-controlled oscillator (VCO) in the PLL may comprise a first voltage to current converter and a second voltage to current converter. The trans-conductance of the first voltage to current converter is 1/β of that of the second voltage to current converter, wherein β>1. The first voltage to current converter is controlled by an output voltage of a loop filter in the PLL, and the second voltage to current converter is controlled by a relative DC voltage, which may be the junction node between R1 and C1 in a loop filer of the PLL. Capacitor multiplication technique may use an auxiliary charge pump to charge or discharge the junction node between R1 and C1 inversely to the main charge pump. When the charge or discharge current unit of the auxiliary charge pump is α times of the main charge pump, the capacitance of C1 may be reduced to just (1−α) times of what it needed in a conventional loop stability compensation method, wherein α<1.