The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2011

Filed:

Jun. 18, 2009
Applicants:

Swarnal Borthakur, Boise, ID (US);

Andy Perkins, Boise, ID (US);

Rick Lake, Meridian, ID (US);

Marc Sulfridge, Boise, ID (US);

Inventors:

Swarnal Borthakur, Boise, ID (US);

Andy Perkins, Boise, ID (US);

Rick Lake, Meridian, ID (US);

Marc Sulfridge, Boise, ID (US);

Assignee:

Aptina Imaging Corporation, George Town, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A wafer of integrated circuits may be bonded to a carrier wafer using a layer of bonding material. The thickness of the wafer of integrated circuits may then be reduced using a series of grinding operations. After grinding, backside processing operations may be performed to form scribe channels that separate the die from each other and to form through-wafer vias. The scribe channels may be formed by dry etching and may have rectangular shapes, circular shapes, or other shapes. A pick and place tool may have a heated head. The bonding layer material may be based on a thermoplastic or other material that can be released by application of heat by the heated head of the pick and place tool. The pick and place tool may individually debond each of the integrated circuits from the carrier wafer and may mount the debonded circuits in packages.


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