The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7987439 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 26, 2011

Filed:

Feb. 07, 2008
Applicants:

Hong BO Che, Pohang, KR;

Young Hwan Kim, Pohang, KR;

Inventors:

Hong Bo Che, Pohang, KR;

Young Hwan Kim, Pohang, KR;

Assignee:

Postech Academy-Industry Foundation, Pohang, Kyungsangbuk-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided are a method and apparatus for analyzing a circuit model by reducing, and a computer program product for analyzing the circuit model. The circuit model at least includes independent current source models, resistance models, and capacitance models. Also, the circuit model forms a resistance capacitance (RC) network with independent current sources. The method includes selecting a node to be removed using resistance information and comparing conductance of a capacitor for a given time step and the total conductance of the node. Further, the method includes removing the selected nodes and generating RC elements and independent current sources using adjacent nodes, which maintain the accuracy of node voltages of a circuit reduced in an accuracy order used for entrywise perturbation of the corresponding circuit equation. Moreover, an efficient method of handling the independent current sources while reducing the circuit is provided.


Find Patent Forward Citations

Che, Hong. (2011). Method and apparatus for analyzing circuit model by reduction and computer program product for analyzing the circuit model (U.S. Patent No. 7987439). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7987439

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