The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 26, 2011

Filed:

Jan. 02, 2008
Applicants:

Ghobad Heidari-bateni, San Diego, CA (US);

Khawza Iftekhar-uddin Ahmed, San Diego, CA (US);

Inventors:

Ghobad Heidari-Bateni, San Diego, CA (US);

Khawza Iftekhar-Uddin Ahmed, San Diego, CA (US);

Assignee:

Olympus Corporation, Hachioji-Shi, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01S 1/24 (2006.01); G01S 13/08 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system and method for estimating the range between two devices performs two or more ranging estimates with subsequent estimates performed using a clock that is offset in phase with respect to a prior estimate. The subsequent estimate allows estimate uncertainties due to a finite clock resolution to be reduced and can yield a range estimate with a higher degree of confidence. In one embodiment, these additional ranging estimates are performed at n/N (for n=1, . . . N−1, with N>1 and a positive integer) clock-period offset introduced in the device. The clock-period offset can be implemented using a number of approaches, and the effect of clock drift in the devices due to relative clock-frequency offset can also be determined. To eliminate the bias due to clock-frequency offset, a system and method to estimate the clock-frequency offset is also presented.


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