The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 26, 2011
Filed:
Oct. 21, 2008
Chua-chin Wang, Kaohsiung, TW;
Wei-chih Chang, Kaohsiung, TW;
Tzung-je Lee, Kaohsiung, TW;
Kuo-chan Huang, Tainan County, TW;
Chua-Chin Wang, Kaohsiung, TW;
Wei-Chih Chang, Kaohsiung, TW;
Tzung-Je Lee, Kaohsiung, TW;
Kuo-Chan Huang, Tainan County, TW;
Himax Technologies Limited, Tainan County, TW;
National Sun Yat-Sen University, Kaohsiung, TW;
Abstract
A mixed-voltage input/output (I/O) buffer includes an output buffer circuit. The output buffer circuit includes an output stage circuit, a gate-tracking circuit and a floating N-well circuit. The output stage circuit includes stacked pull-up P-type transistors and stacked pull-down N-type transistors, in which a first P-type transistor of the stacked pull-up P-type transistors and a first N-type transistor of the stacked pull-down N-type transistors are coupled to an I/O pad. The gate-tracking circuit controls gate voltage of the first P-type transistor in accordance with a voltage of the I/O pad to prevent leakage current. The floating N-well circuit provides N-well voltages for an N-well of the first P-type transistor and an N-well of a second P-type transistor, controlling gate voltage of the first P-type transistor, of the gate-tracking circuit to prevent leakage current.