The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 26, 2011
Filed:
Sep. 11, 2008
Jong Tae Moon, Daejeon, KR;
Yong Sung Eom, Daejeon, KR;
Min Ji Lee, Daejeon, KR;
Hyun Kyu Yu, Daejeon, KR;
Jong Tae Moon, Daejeon, KR;
Yong Sung Eom, Daejeon, KR;
Min Ji Lee, Daejeon, KR;
Hyun Kyu Yu, Daejeon, KR;
Electronics and Telecommunications Research Institute, Daejeon, KR;
Abstract
Provided are a wafer level package in which a communication line can be readily formed between an internal device and the outside of the package, and a method of fabricating the wafer level package. The wafer level package includes a first substrate having a cavity in which a first internal device is disposed, an Input/Output (I/O) pad formed on the first substrate and electrically connected with the first internal device, a second substrate disposed over the first substrate and from which a part corresponding to the I/O pad is removed, and a solder bonding the first and second substrates. According to the wafer level package and the method of fabricating the same, upper and lower substrates are sawed to different cutting widths, or a hole is formed in the upper substrate, such that a communication line of an internal device can be readily formed without a via process which penetrates a substrate. Therefore, in comparison with a conventional wafer level package fabricated using the via process, it is possible to simplify a fabrication process and reduce production cost.