The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 26, 2011

Filed:

Nov. 26, 2008
Applicants:

Fumito Isaka, Kanagawa, JP;

Sho Kato, Kanagawa, JP;

Kosei Nei, Kanagawa, JP;

Ryu Komatsu, Kanagawa, JP;

Akihisa Shimomura, Kanagawa, JP;

Koji Dairiki, Kanagawa, JP;

Inventors:

Fumito Isaka, Kanagawa, JP;

Sho Kato, Kanagawa, JP;

Kosei Nei, Kanagawa, JP;

Ryu Komatsu, Kanagawa, JP;

Akihisa Shimomura, Kanagawa, JP;

Koji Dairiki, Kanagawa, JP;

Assignee:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A photoelectric conversion device having an excellent photoelectric conversion characteristic is provided while effectively utilizing limited resources. A fragile layer is formed in a region at a depth of less than 1000 nm from one surface of a single crystal semiconductor substrate, and a first impurity semiconductor layer, a first electrode, and an insulating layer are formed on the one surface side of the single crystal semiconductor substrate. After bonding the insulating layer to a supporting substrate, the single crystal semiconductor substrate is separated with the fragile layer or its vicinity used as a separation plane, thereby forming a first single crystal semiconductor layer over the supporting substrate. A second single crystal semiconductor layer is formed by epitaxially growing a semiconductor layer on the first single crystal semiconductor layer in accordance with a plasma CVD method in which a silane based gas and hydrogen with a flow rate 50 times or more that of the silane gas are used as a source gas. A second impurity semiconductor layer which has a conductivity type opposite to that of the first impurity semiconductor layer is formed over the second single crystal semiconductor layer. A second electrode is formed over the second impurity semiconductor layer.


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