The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 26, 2011

Filed:

Feb. 04, 2008
Applicants:

Francis Gabriel Celii, Dallas, TX (US);

Robert Kraft, Plano, TX (US);

Kezhakkedath R. Udayakumar, Dallas, TX (US);

Scott Robert Summerfelt, Garland, TX (US);

Theodore S. Moise, Dallas, TX (US);

Inventors:

Francis Gabriel Celii, Dallas, TX (US);

Robert Kraft, Plano, TX (US);

Kezhakkedath R. Udayakumar, Dallas, TX (US);

Scott Robert Summerfelt, Garland, TX (US);

Theodore S. Moise, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.


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