Integrated circuit device including a circuit to generate error correction code for correcting error bit for each of memory circuits

Abstract

An integrated circuit device includes a plurality of memory circuits, a memory hibernation state control circuit to bring the memory circuits into a hibernation state in response to an external command, a state controller which indicates an interrupt in a memory circuit in a hibernation state, and a plurality of partial error checking and correcting (ECC) code generating circuits which are provided for the memory circuits, respectively, to code hold data of an address of a memory circuit in a hibernation state in accordance with a rule of a Hamming code determinant by an interrupt in the memory circuit in the hibernation state. The integrated circuit device further includes a code storage memory which obtains ECC code data corresponding to all of the hold data based on partial ECC codes coded by the partial ECC code generating circuit and stores the ECC code data in a corresponding address.