The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 19, 2011
Filed:
Sep. 04, 2007
Luis A. Lastras-montano, Cortlandt Manor, NY (US);
Darren L. Anand, Williston, VT (US);
Jeffrey H. Dreibelbis, Williston, VT (US);
Charles A. Kilmer, Essex Junction, VT (US);
Warren E. Maule, Cedar Park, TX (US);
Robert B. Tremaine, Stormville, NY (US);
Luis A. Lastras-Montano, Cortlandt Manor, NY (US);
Darren L. Anand, Williston, VT (US);
Jeffrey H. Dreibelbis, Williston, VT (US);
Charles A. Kilmer, Essex Junction, VT (US);
Warren E. Maule, Cedar Park, TX (US);
Robert B. Tremaine, Stormville, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A system and method for providing DRAM device-level repair via address remappings external to the device. A system includes a memory controller having an interface to one or more memory devices via a memory module. The memory devices include addressable redundant and non-redundant memory blocks. The memory controller also includes a mechanism for utilizing one or more redundant memory blocks in place of one or more failing non-redundant memory blocks via an address remapping external to the memory device. The remapping occurs while the system is on-line.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile