The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2011

Filed:

Aug. 02, 2010
Applicants:

Seyed Jafar Jafarian-tehrani, Fremont, CA (US);

Ralph Jan-pin LU, Fremont, CA (US);

Inventors:

Seyed Jafar Jafarian-Tehrani, Fremont, CA (US);

Ralph Jan-Pin Lu, Fremont, CA (US);

Assignee:

Lam Research Corporation, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/683 (2006.01); H01T 23/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An arrangement for securing a wafer during substrate processing is provided. The arrangement includes a power supply and an electrostatic chuck (ESC). The ESC supports the wafer and includes a positive and a negative terminal. A positive high voltage is provided to the positive terminal through an RF filter and a negative high voltage is provided to the negative terminal through the RF filter. The arrangement also includes a first and a second trans-impedance amplifiers (TIAs) that measure a first set of voltages for determining a value of a positive load current applied to the positive terminal and a third and fourth TIAs that measure a second set of voltages for determining a value of a negative load current applied to the negative terminal. The arrangement yet also includes a program to adjust a bias voltage using the values of the positive load current and the negative load current.


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