The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2011

Filed:

Jan. 09, 2007
Applicant:

Yoshiaki Kato, Shiga, JP;

Inventor:

Yoshiaki Kato, Shiga, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N 3/14 (2006.01); H04N 5/335 (2006.01);
U.S. Cl.
CPC ...
Abstract

To provide a solid-state imaging apparatus which is capable of preventing electric charge from being injected from a semiconductor substrate while electric charge is being accumulated into photodiodes. The solid-state imaging apparatus includes a solid-state imaging device and a driving pulse control unit. The solid-state imaging device includes: a semiconductor substrate, photodiodes which are two-dimensionally formed on the semiconductor substrate, and vertical Charge-coupled devices (CCDs) having at least one arranged read-out gate and non-read-out gate for each of the photodiodes, the read-out gate being for reading out accumulated electric charge from the associated photodiode, and the non-read-out gate being not for reading out accumulated electric charge from the associated photodiode. The driving pulse control unit applies driving pulses sequentially to the respective read-out gates in order to change the read-out gates from stand-by LOW-voltage states to MIDDLE-voltage states, and apply a driving pulse for maintaining a LOW-voltage state of at least one of non-read-out gates adjacent to a last read-out gate in the order of the change among the non-read-out gates, during the change starting with a first read-out gate and ending with the last read-out gate.


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