The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2011

Filed:

Aug. 22, 2007
Applicants:

Alexander A. Danilin, Eindhoven, NL;

Martinus T. Bennebroek, Den Bosch, NL;

Sergei V. Sawitzki, Veldhoven, NL;

Inventors:

Alexander A. Danilin, Eindhoven, NL;

Martinus T. Bennebroek, Den Bosch, NL;

Sergei V. Sawitzki, Veldhoven, NL;

Assignee:

ST-Ericsson SA, Geneva, CH;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

The configurable logic device comprises a plurality of configurable logic cells (). A configurable logic cell comprises a plurality of multi-bit registers (). At least one is accessible both in a parallel and in a serial fashion. A functional unit () therein is coupled to two or more of the registers and comprises a chain of functional unit segments (') that each comprise an AND gate () and a 1-bit full adder () receiving an output of the AND-gate. An output selection facility () provides an output signal of the configurable logic cell selected from two or more input signals. At least one of the input signals is provided by one of the multi-bit registers, and another by the functional unit.


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