The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7982477 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 19, 2011

Filed:

Aug. 01, 2008
Applicant:

Michael M. Ghadaksaz, Inverness, IL (US);

Inventor:

Michael M. Ghadaksaz, Inverness, IL (US);

Assignee:

AES Technologies, Inc., Schaumburg, IL (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/10 (2006.01); G01R 31/26 (2006.01);
U.S. Cl.
CPC ...
Abstract

A universal test fixture for testing and characterization of high-power flange-packaged RF and microwave transistors and diodes includes a precision-machined heat sink having a built-in center cavity with a finger catch on either side of the cavity which uses a plurality of matching modules that are installed in the center cavity and designed as transistor or diode carrier modules to provide mounting for the high-power packaged RF and microwave devices in a wide variety of flange type packages, an adjustable clamping structure connected to a movable arm, and a plurality of non-conductive high temperature pressure clamps. Each carrier module is made of a gold-plated rectangular aluminum block having a center cavity that is machined to the package outline. A non-conductive black-anodized high-temperature resistant pressure clamp machined to the package outline holds the packaged device in the carrier module. When clamped down using the clamping structure, the pressure clamp holds the package leads on a printed circuit board ensuring excellent electrical contact between package leads and circuit traces and surrounding ground planes, obviating soldering and desoldering the leads to the circuit board. The pressure clamp also produces pressure along the device package to hold the packaged device to the carrier module which houses the device and which itself is bolted to the heat sink resulting in excellent thermal contact under the device.


Find Patent Forward Citations

Ghadaksaz, Michael. (2011). Universal test fixture for high-power packaged transistors and diodes (U.S. Patent No. 7982477). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7982477

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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