The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 19, 2011
Filed:
Mar. 09, 2007
Atsuo Watanabe, Hitachiota, JP;
Mitsutoshi Honda, Hitachi, JP;
Norio Ishitsuka, Kasumigaura, JP;
Masahiro Ito, Hitachi, JP;
Toshihito Tabata, Hitachinaka, JP;
Shinichi Kurita, Mito, JP;
Hidekazu Kamioka, Hitachi, JP;
Atsuo Watanabe, Hitachiota, JP;
Mitsutoshi Honda, Hitachi, JP;
Norio Ishitsuka, Kasumigaura, JP;
Masahiro Ito, Hitachi, JP;
Toshihito Tabata, Hitachinaka, JP;
Shinichi Kurita, Mito, JP;
Hidekazu Kamioka, Hitachi, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
A dielectrically isolated semiconductor device of high reliability is provided by realizing a fine and deep element isolating region which can prevent dislocation of an oxide film as an insulation layer by oxidation-induced stress. The dielectrically isolated semiconductor device includes an SOI substrate supporting an active element layer deeper than an expanded distance of a depletion layer subjected to the highest voltage applied to the device, and an element isolating region which encloses the active element layer. The element isolating region contains a deep trench which comes into contact with the insulation layer, and which is filled with n heavily doped layers on both side walls, second insulation films each adjacent to the n heavily doped layer and a polycrystalline semiconductor layer formed between the second insulation films.