The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2011

Filed:

Jul. 24, 2009
Applicants:

Shigeru Mori, Tokyo, JP;

Takahiro Korenari, Tokyo, JP;

Tadahiro Matsuzaki, Tokyo, JP;

Hiroshi Tanabe, Tokyo, JP;

Inventors:

Shigeru Mori, Tokyo, JP;

Takahiro Korenari, Tokyo, JP;

Tadahiro Matsuzaki, Tokyo, JP;

Hiroshi Tanabe, Tokyo, JP;

Assignees:

NEC Corporation, Tokyo, JP;

NEC LCD Technologies, Ltd, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/31 (2006.01);
U.S. Cl.
CPC ...
Abstract

A base layer is formed on an insulating substrate, and a semiconductor layer is formed in localized fashion thereon. A gate insulating film is then formed so as to cover the semiconductor layer, and a gate electrode is formed on a portion of the gate insulating film. An impurity is then implanted into the semiconductor layer via the gate insulating film, and a source region, a drain region, and an LDD region are formed. The gate insulating film is etched with dilute hydrofluoric acid. An electrode-protecting insulating film is then formed so as to cover the gate electrode, and the entire surface of the surface layer portion of the electrode-protecting insulating film is etched away using dilute hydrofluoric acid. Carrier traps introduced into the electrode-protecting insulating film and the gate insulating film are thereby removed.


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