The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 2011
Filed:
Feb. 15, 2008
Christopher J. Berry, Hudson, NY (US);
Jose Luis Pontes Correia Neves, Poughkeepsie, NY (US);
Lawrence David Curley, Round Rock, TX (US);
Patrick James Meaney, Poughkeepsie, NY (US);
Travis Wellington Pouarz, Austin, TX (US);
William J. Scarpero, Jr., Poughkeepsie, NY (US);
Christopher J. Berry, Hudson, NY (US);
Jose Luis Pontes Correia Neves, Poughkeepsie, NY (US);
Lawrence David Curley, Round Rock, TX (US);
Patrick James Meaney, Poughkeepsie, NY (US);
Travis Wellington Pouarz, Austin, TX (US);
William J. Scarpero, Jr., Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The process of laying out a floorplan for a clock control distribution network in an integrated chip design is simplified and the efficiency of a staging network created is improved. Rather than manually create the staging network in HDL or as a network description table while looking at a picture of the chip floorplan in a Cadence Viewer, an automated method which runs in the Cadence environment uses an algorithmic approach to the problem of maximizing the utilization of staging latches, eliminating unnecessary power and area usage. Efficiency is maximized by updating the Physical Layout directly with the staging solution arrived at by the algorithm.