The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 2011
Filed:
Nov. 17, 2008
Applicant:
Sankaranarayanan Srinivasan, San Jose, CA (US);
Inventor:
Sankaranarayanan Srinivasan, San Jose, CA (US);
Assignee:
Xilinx, Inc., San Jose, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
Circuit placement for increasing circuit packing density for an integrated circuit is described. A design is synthesized and mapped. Components of the design are placed to provide a first placed design. A congestion density map is generated for the first placed design. A congestion region in the congestion density map is identified and targeted for determining if the first placed design has a control set conflict. A first circuit object associated with the control set conflict is selected and either re-placed or re-synthesized to at least diminish the control set conflict.