The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 2011
Filed:
Jan. 08, 2009
Michael J. Carnevale, Rochester, MN (US);
Elianne A. Bravo, Wappingers Falls, NY (US);
Kevin C. Gower, LaGrangeville, NY (US);
Gary A. Van Huben, Poughkeepsie, NY (US);
Donald J. Ziebarth, Rochester, MN (US);
Michael J. Carnevale, Rochester, MN (US);
Elianne A. Bravo, Wappingers Falls, NY (US);
Kevin C. Gower, LaGrangeville, NY (US);
Gary A. Van Huben, Poughkeepsie, NY (US);
Donald J. Ziebarth, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A memory hub device with test logic is configured to communicate with memory devices via multiple hub device ports, and is also configured to communicate on one or more busses in an upstream and downstream direction. The test logic includes a built-in self test apparatus providing logic to simultaneously and independently test the memory devices interfaced to one or more of the hub device ports using read and write data patterns. The test logic also includes configuration registers to hold fault and diagnostic information, and to initiate one or more tests. The memory hub device can further include command collision detection logic, a trace array, buffer transmit mode logic, trigger logic, clock adjustment logic, transparent mode logic, and a configured command sequencer, as well as additional features.