The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 2011
Filed:
Jan. 08, 2009
Paul L. Master, Sunnyvale, CA (US);
Eugene Hogenauer, San Carlos, CA (US);
Bicheng William Wu, Union City, CA (US);
Dan Minglun Chuang, San Jose, CA (US);
Bjorn Freeman Benson, Seattle, WA (US);
Paul L. Master, Sunnyvale, CA (US);
Eugene Hogenauer, San Carlos, CA (US);
Bicheng William Wu, Union City, CA (US);
Dan MingLun Chuang, San Jose, CA (US);
Bjorn Freeman Benson, Seattle, WA (US);
QST Holding, LLC, Palo Alto, CA (US);
Abstract
A method, system and program are provided for development of an adaptive computing integrated circuit and corresponding configuration information, in which the configuration information provides an operating mode to the adaptive computing integrated circuit. The exemplary system includes a scheduler, a memory, and a compiler. The scheduler is capable of scheduling a selected algorithm with a plurality of adaptive computing descriptive objects to produce a scheduled algorithm and a selected adaptive computing circuit version. The memory is utilized to store the plurality of adaptive computing descriptive objects and a plurality of adaptive computing circuit versions generated during the scheduling process. The selected adaptive computing circuit version is converted into a hardware description language, for fabrication into the adaptive computing integrated circuit. The compiler generates the configuration information, from the scheduled algorithm and the selected adaptive computing circuit version, for the performance of the algorithm by the adaptive computing integrated circuit. In the exemplary embodiments, multiple versions of configuration information may be generated, for different circuit versions, different feature sets, different operating conditions, and different operating modes.