The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2011

Filed:

Oct. 18, 2010
Applicants:

Dong-gyu Kim, Sunwon, KR;

Jun-ho Song, Suwon, KR;

Jong-woong Chang, Suwon, KR;

Jae-ho Choi, Seoul, KR;

Byoung-sun NA, Suwon, KR;

Young-bae Park, Yongin, KR;

Sung-wook Huh, Seoul, KR;

Inventors:

Dong-Gyu Kim, Sunwon, KR;

Jun-Ho Song, Suwon, KR;

Jong-Woong Chang, Suwon, KR;

Jae-Ho Choi, Seoul, KR;

Byoung-Sun Na, Suwon, KR;

Young-Bae Park, Yongin, KR;

Sung-Wook Huh, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/136 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for manufacturing a thin film transistor array panel is disclosed. A gate wiring pattern is formed on an insulating substrate. A gate insulating layer is formed on the gate wiring pattern. A semiconductor pattern is formed on the gate insulating layer. A transparent conductive layer is formed on the gate insulating layer. The transparent conductive layer is patterned to form a pixel electrode. An opening is formed at a circumference of the pixel electrode. The opening minimizes misalignment during the manufacturing process and prevents shorts between a data line and the pixel electrode.


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