The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 2011
Filed:
Sep. 03, 2004
Amar Patel, Redmond, WA (US);
Charles N. Boyd, Woodinville, WA (US);
David R. Blythe, Kirkland, WA (US);
Jeff M. J. Noyle, Kirkland, WA (US);
Michael A. Toelle, Bellevue, WA (US);
Stephen Harry Wright, Bothell, WA (US);
Amar Patel, Redmond, WA (US);
Charles N. Boyd, Woodinville, WA (US);
David R. Blythe, Kirkland, WA (US);
Jeff M. J. Noyle, Kirkland, WA (US);
Michael A. Toelle, Bellevue, WA (US);
Stephen Harry Wright, Bothell, WA (US);
Microsoft Corporation, Redmond, WA (US);
Abstract
An enhanced graphics pipeline is provided that enables common core hardware to perform as different components of the graphics pipeline, programmability of primitives including lines and triangles by a component in the pipeline, and a stream output before or simultaneously with the rendering a graphical display with the data in the pipeline. The programmer does not have to optimize the code, as the common core will balance the load of functions necessary and dynamically allocate those instructions on the common core hardware. The programmer may program primitives using algorithms to simplify all vertex calculations by substituting with topology made with lines and triangles. The programmer takes the calculated output data and can read it before or while it is being rendered. Thus, a programmer has greater flexibility in programming. By using the enhanced graphics pipeline, the programmer can optimize the usage of the hardware in the pipeline, program vertex, line or triangle topologies altogether rather than each vertex alone, and read any calculated data from memory where the pipeline can output the calculated information.