Algorithmic analog-to-digital conversion

Abstract

A 1.5-bit algorithmic analog-to-digital converter (ADC) generates a digital value representative of an input voltage. The ADC implements a series of conversion cycles for a conversion operation. Each conversion cycle has three sub-cycles: a scaling sub-cycle, a first sample sub-cycle, and a second sample sub-cycle. In the scaling sub-cycle, the residual voltage from the previous conversion cycle is doubled to generate a first voltage. In the first sample sub-cycle, a first bit of a corresponding bit pair is determined based on the polarity of the first voltage. The first voltage is either increased or decreased by a reference voltage based on the polarity of the first voltage to generate a second voltage. In the second sample sub-cycle, a second bit of the corresponding bit pair is determined based on the polarity of the second voltage. The second voltage then is either increased or decreased by the reference voltage based on the polarity of the second voltage to generate the residual voltage used for the next conversion cycle in the series. Each bit pair is mapped to a corresponding two-bit code value and the resulting code values are used to generate the digital value.