The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 2011
Filed:
Sep. 25, 2008
Raymond A. Bertram, Austin, TX (US);
Mark J. Brazell, Cedar Park, TX (US);
Vanessa S. Canac, Austin, TX (US);
Darius D. Gaskins, Austin, TX (US);
James R. Lundberg, Austin, TX (US);
Matthew Russell Nixon, Austin, TX (US);
Raymond A. Bertram, Austin, TX (US);
Mark J. Brazell, Cedar Park, TX (US);
Vanessa S. Canac, Austin, TX (US);
Darius D. Gaskins, Austin, TX (US);
James R. Lundberg, Austin, TX (US);
Matthew Russell Nixon, Austin, TX (US);
VIA Technologies, Inc., New Taipei, TW;
Abstract
A microprocessor according to one embodiment includes a supply node providing a core voltage, a functional block, a charge node, select logic, and substrate bias logic. The functional block has multiple power modes and includes one or more semiconductor devices and a substrate bias rail routed within the functional block and coupled to a substrate connection of at least one semiconductor device. The select logic couples the substrate bias rail to the charge node when the functional block is in a low power mode and clamps the substrate bias rail to the supply node when the functional block is in a full power mode. The substrate bias logic charges the charge node to a bias voltage at an offset voltage relative to the core voltage when the functional block is in the low power mode. Semiconductor devices may be provided to clamp or otherwise couple the bias rail.