Delay adjusting method, and delay circuit

Abstract

A variable delay circuitincludes: a multistage delay circuitconstructed by connecting delay elements Dto Dn in series; a selecting unitwhich selects one delayed signal obtained by introducing different amounts of delay by passing a reference clock through one or more of the delay elements Dto Dn; a decision unitwhich, at decision timing synchronized to the reference clock, makes a decision on the logic state of each delayed signal sequentially selected from among the plurality of delayed signals; and a changing point detection unitwhich detects at least two delay elements Dm and Dk where a change has occurred in the logic state of the reference clock at the decision timing, and wherein the difference (k−m) between the numbers of delay elements through which the clock signal has passed until reaching one of the two detected delay elements Dm and Dk is used as the number of delay elements that provides a desired delay time.