The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 2011
Filed:
Oct. 30, 2010
Kiyoto Ito, Kokubunji, JP;
Makoto Saen, Kodaira, JP;
Yuki Kuroda, Tachikawa, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSIand a memory LSIare stacked and the processor LSIand the memory LSIin the same combination are stacked adjacent to each other in the vertical direction. Communication between the processor LSIand the memory LSIin the same combination is performed by a dedicated electrode provided therebetween, and communication between processor LSIsand communication from the processor LSIto the outside are performed by a through silicon via for signalwhich passes through all the LSIs.