The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2011

Filed:

Mar. 23, 2009
Applicants:

Takeshi Takeda, Kanagawa, JP;

Yukihiro Ando, Kanagawa, JP;

Masaki Okamoto, Kanagawa, JP;

Masayuki Okada, Kanagawa, JP;

Kaori Takimoto, Kanagawa, JP;

Katsuhisa Kugimiya, Kanagawa, JP;

Tadayuki Kimura, Kanagawa, JP;

Inventors:

Takeshi Takeda, Kanagawa, JP;

Yukihiro Ando, Kanagawa, JP;

Masaki Okamoto, Kanagawa, JP;

Masayuki Okada, Kanagawa, JP;

Kaori Takimoto, Kanagawa, JP;

Katsuhisa Kugimiya, Kanagawa, JP;

Tadayuki Kimura, Kanagawa, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for producing a solid-state imaging device includes steps of: forming transfer electrodes on a substrate having a plurality of light-sensing portions through a gate insulating layer so that the light-sensing portions are exposed; forming a planarized insulating layer on the substrate to cover the transfer electrodes formed on the substrate; forming openings in the planarized insulating layer so that each of the transfer electrodes is partly exposed out of the planarized insulating layer at a predetermined position; forming a wiring material layer so that the openings are filled with the wiring material layer; forming a resist layer on the wiring material layer; exposing and developing the resist layer so that only the resist layer in a predetermined area covering the openings is left; and patterning the wiring material layer using the exposed and developed resist layer to form connection wirings connected to the transfer electrodes by the openings.


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